“Error Recovery Within Integrated Circuit,” K. Flautner, T. Austin, D. Blaauw, T. Mudge, D. Bull. USPTO Number: 8,650,470. February 11, 2014. [pdf]
2013
“Crossbar Circuitry and Method of Operation of Such Crossbar Circuitry”, S. Satpathy, D. Blaauw, T. Mudge, D. Sylvester, R. Dreslinski. USPTO Number: 8,549,207; 8,255,610; 8,230,152; 8,108,585. October 31, 2013; August 28, 2012; July 24, 2012; January 31, 2012.[pdf][pdf][pdf][pdf]
“Error Recovery Within Processing Stages of an Integrated Circuit,” K. Flautner, T. Austin, D. Blaauw, T. Mudge, D. Bull. USPTO Number: 8,407,537. March 26, 2013. [pdf]
“Vertical Interconnect Patterns in Multi-Layer Integrated Circuits”, D. Blaauw, T. Mudge, D. Sylvester, R. Dreslinski Jr. USPTO Number: 8,381,155. February 19, 2013. [pdf]
“Random Number Generator”, T. Mudge, D. Blaauw, C. Tokunaga. USPTO Number: 8,346,832. January 1, 2013. [pdf]
2012
“Cache Memory System for a Data Processing Apparatus” ,R. Dreslinski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester. USPTO Number: 8,335,122. December 18, 2012. [pdf]
“Cache Memory with Power Saving State”, T. Mudge, D. Roberts, T. Wenisch. USPTO Number: 8,285,936. October 9, 2012. [pdf]
“Crossbar Circuitry and Method of Operation of Such Crossbar Circuitry”, S. Satpathy, D. Blaauw, T. Mudge, D. Sylvester, R. Dreslinski. (Japan) Patent Number 5074538. August 31, 2012.
“Random Number Generator”, T. Mudge, D. Blaauw, C. Tokunaga. (Japan) Patent Number 4938612. August 14, 2013.
“Error Recovery Within Processing Stages of an Integrated Circuit”, K. Flautner, T. Austin, D. Blaauw, T. Mudge. USPTO Number: 8,185,786. May 22, 2012. [pdf]
“Priority Arbitration Control Within Interconnect Circuitry”, S. Satpathy, D. Blaauw, D. Sylvester, T. Mudge. Appllcation Number: 13/,438,920. April 4, 2012. [pdf]
“Storage of Data in Data Stores Having Some Faulty Storage Locations”, T. Mudge, G. Dasika, D. Roberts. USPTO Number: 8,145,960, 8,230,277. March 27, 2012; July 24, 2012. [pdf][pdf]
2011
“Crossbar Circuitry for Applying an Adaptive Priority Scheme and Method of Operation of Such Crossbar Circuitry”, S. Satpathy, T. Mudge, D. Sylvester, D. Blaauw. Application Number: 12/926,462. June 16, 2011. [pdf]
“Random Number Generator”, T. Mudge, D. Blaauw, C. Tokunaga. United Kindgom Number: GB2442838. May 11, 2011.
“Cost Effective Razor Pipeline Recovery with Micro-Architectural Support,” T. Mudge, K. Flautner, D. Blaauw, T. Austin, D. Bull, S. Das. (Japan) Patent Number 4722994. April 15, 2011. (Same title in China, United Kingdom) .
“Data Retention Latch Provision Within Integrated Circuits”, T. Mudge. Patent Number: 168514 (Israel). February 1, 2011.
2010
“Error Recovery Within Integrated Circuit,” K. Flautner, T. Austin, D. Blaauw, T. Mudge, D. Bull. Application Number: 12/926,084. [pdf]
“Integrated Circuit with error Correction Mechanisms to Offset Narrow Tolerancing Razor Technology”, T. Mudge, K. Flautner, D. Blaauw, T. Austin, David Bull. USPTO Number: 7,701,240. April 20, 2010. [pdf]
“Error Detection and recovery within Processing Stages of an Integrated Circuit”, K. Flautner, T. Austin, D. Blaauw, T. Mudge. USPTO Number: 7,650,551. January 19, 2010. (Same title in Israel and the Republic of Korea). [pdf]
2009
“Memory Control”, D. Roberts, T. Mudge, T. Wenisch. Application Number: 12/588,592. October 20, 2009. [pdf]
“Data Processor Memory Circuit”, K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge. USPTO Number: 7,533,226. May 12, 2009. [pdf]
“Performance level selection in a data processing system by combining a plurality of performance requests”, K. Flautner, T. Mudge. USPTO Number: 7,512,820. March 31, 2009. [pdf]
“Using Shadow Latches As Low Leakage Retention Latches”, K. Flautner, D. Blaauw, T. Austin, T. Mudge. China ZL200480007397. March 11, 2009. (Same title in Japan).
2008
“Systematic and random error detection and recovery within processing stages of an integrated circuit”, T. Austin, D. Blaauw, K. Flautner, T. Mudge. USPTO Number: 7,337,356. February 26, 2008. (Same title in Europe). [pdf]
“Performance counter for adding variable work increment value that is dependent upon clock frequency”, T. Mudge, K. Flautner, D. Flynn. USPTO Number: 7,321,942. January 22, 2008. [pdf]
2007
“Data Retention Latch Provision Within Integrated Circuits”, T. Mudge, T. Austin, D. Blaauw, K. Flautner. USPTO Number: 7,310,755. December 18, 2007. [pdf]
“Error Detection and Recovery Within Processing Stages of an Integrated Circuit”, K. Flautner, T. Austin, D. Blaauw, T. Mudge. USPTO Number: 7,278,080. October 2, 2007. [pdf]
“Data Processor Memory Circuit”, K. Flautner, T. N. Mudge. USPTO Number: 7,260,694. August 21, 2007. [pdf]
“Performance Level Setting of a Data Processing System”, K. Flautner, T. N. Mudge. USPTO Number: 7,194,385. March 20, 2007. [pdf]
“Systematic and Random Error Detection and Recovery Within Processing Stages of an Integrated Circuit”, T. N. Mudge, T. M. Austin, D. T. Blaauw, K. Flautner. USPTO Number: 7,162,661. January 9, 2007. [pdf]
2006
“Performance Level Selection in a Data Processing System Using a Plurality of Performance Request Calculating Algorithms”, K. Flautner, T. N. Mudge. USPTO Number: 7,131,015. October 31, 2006. [pdf]
“Memory System Having Fast and Slow Data Reading Mechanisms”, T. M. Austin, D. T. Blaauw, T. N. Mudge, D. M. Sylvester, K. Flautner. USPTO Number: 7,072,229. July 4, 2006. [pdf]
“Data Processor Memory Circuit”, K. Flautner, D. T. Blaauw, T. N. Mudge, N. S. Kim, S. M. Martin. USPTO Number: 7,055,007. May 30, 2006. [pdf]
2005
“Memory System Having Fast and Slow Data Reading Mechanisms”, T. N. Mudge, T. M. Austin, D. T. Blaauw, D. M. Sylvester, K. Flautner. USPTO Number: 6,944,067. September 13, 2005. [pdf]
1985
“Design Rule Checking Using Serial Neighborhood Processors”, R. M. Lougheed, T. N. Mudge. USPTO Number: 4,510,616. April 9, 1985. [pdf]
1984
“Design Rule Checking Using Serial Neighborhood Processors”, R. M. Lougheed, T. N. Mudge. USPTO Number: 4,441,207. April 3, 1984. [copy of M.S. thesis] [pdf]
