Publications

Listed below are publications organized by year.

To Appear

  • B. Oh, N. S. Kim, J. Ahn, B. Li, R. Dreslinski and T. Mudge. Configurable-ECC: Improving Load Balancing for HBM Channels. MEMSYS, Washington DC, October 2018.

2018

  • S. Pal, J. Beaumont, D-H. Park, A. Amarnath, S. Feng, C. Chakrabarti, H-S. Kim, D. Blaauw, T. Mudge, R. Dreslinski. OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator. Int. Symp. on High Performance Computer Architecture (HPCA),Vienna, austria, February 2018, pp. 724-736.

2017

  • D-H. Park, J Beaumont, T. Mudge. Accelerating Smith-Waterman Alignment workload with Scalable Vector Computing. REV-A Workshop at IEEE Cluster, Hawaii, September 2017, pp. 8.
  • Y. Chen, S. Lu, C. Fu, D. Blaauw, R. Dreslinski, H.-S. Kim, T. Mudge. A Programmable Galois Field Processor for the Internet of Things. Proc. 44th Int. Symp. on Computer Architecture (ISCA), Toronto, Canada, June 2017, pp. 55-68.
  • Y. Kang, J. Hauswald, C. Gao, A. Rovinski, T. Mudge, J. Mars, L. Tang. Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge. Proc. 22nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Xi’an, China, April 2017, pp. 615-629.
  • N. Pinckney, L. Shifren, B. Cline, S. Sinha, S. Jeloka, R. Dreslinski, T. Mudge, D. Sylvester, D. Blaauw. Impact of FinFET on Near-Threshold Voltage Scalability. IEEE Design & Test, March/April 2017, pp. 31-38.
  • S. Bang, J. Wang, Z. Li, C. Gao, Y. Kim, Q. Dong, Y.P. Chen, L. Fick, X. Sun, R.G. Dreslinski, T. Mudge, H-S. Kim, D. Blaauw, D. Sylvester. A 288uW Programmable Deep Learning Processor with 270kB On-chip Weight Storage Using Non-uniform Memory Hierarchy for Mobile Intelligence. 2017 International Solid-State Circuits Conference (ISSCC), San Francisco, CA, February 2017, pp 250-251.

2016

  • H-M. Chen, S. Jeloka, A. Arunkumar, D. Blaauw, C-J. Wu, T. Mudge, C. Chakrabarti. Using Low Cost Erasure and Error Correction Schemes to Improve Reliability of Commodity DRAM Systems. IEEE Transactions on Computers, December 2016, vol. 65, no. 12, pp. 3766-3779.
  • Chen, N. Chiotellis, Li.-X. Chuo, C. Pfeiffer, Y. Shi, R. Dreslinski, A. Grbic, T. Mudge, David D. Wentzloff, D. Blaauw, and H.-S. Kim. Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes. IEEE Journal on Selected Areas in Communications, December 2016, vol. 34, no. 12, pp. 3962-3977.
  • N. Abeyratne, H.-M. Chen, B. Oh, R. Dreslinski, C. Chakrabarti, T. Mudge. Checkpointing Exascale Memory Systems with Existing Memory Technologies. MEMSYS, Washington DC, October 2016, pp. 18-28.
  • H-M. Chen, C-J. Wu, T. Mudge, C. Chakrabarti. RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory. ACM Transactions on Architecture and Code Optimization (TACO), 16, issue 3, September 2016, article 24, 24 pp.
  • T. Mudge, R. Sendag, F. Chong, J. Yi, I. Markov, D. Chiou. Impact of Future Technologies on Architecture. IEEE MICRO, July/August 2016, pp. 48-56.
  • Q. Zheng, Y. Chen, S. Abeyratne, R. Dreslinski, and T. Mudge. Designing General Purpose Cloud Platforms for Future Radio Access Networks. CTN: IEEE CompSoc Technology News http://www.comsoc.org/ctn. July 2016.
  • N. Pinckney, B. Cline, R.G. Dreslinski, S. Jeloka, L. Shifrin, S. Sinha, T. Mudge, D. Sylvester, D. Blaauw. Near-Threshold Computing in FinFET Technologies: Opportunities for Improved Voltage Scalability. 53rd Design Automation Conference (DAC), Austin, TX, June 2016, pp. 1-6.
  • J. Hauswald, M. A. Laurenzano, Y. Zhang, C. Li, A. Rovinski, A. Khurana, R.G. Dreslinski, T. Mudge, V. Petrucci, L. Tang, J. Mars. Sirius Implications For Future Warehouse-scale Computers. IEEE MICRO, May/June 2016, vol. 36, no. 3, pp. 42-53. [Top Pick: selected as one of the 12 best papers in computer architecture for 2015]
  • J. Hauswald, M. A. Laurenzano, Y. Zhang, C. Li, A. Rovinski, A. Khurana, R.G. Dreslinski, T. Mudge, V. Petrucci, L. Tang, J. Mars. Designing Future Warehouse Scale Computers for Sirius, an Open End-to-End Voice and Vision Personal Assistant. ACM Trans. On Computer Systems, 34, 1, Article 2, April 2016, 32 pp.
  • Y. Chen, S. Lu, H-S. Kim, D. Blaauw, R.G. Dreslinski, T. Mudge. A Low Power Software-Defined-Radio Baseband Processor for the Internet of Things. Proc. 22nd IEEE Int. Symp. on High Performance Computer Architecture (HPCA-22), March 2016, Barcelona, Spain, pp. 40-51.

2015

  • Kloosterman, J. Beaumont, M. Wollman, A. Sethia, R.G. Dreslinski, T. Mudge, S. Mahlke. WarpPool: Sharing Requests with Inter-Warp Coalescing for Throughput Processors. The 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Hawaii, December 2015, pp. 433-444.
  • H-M. Chen, A. Arunkumar, C-J. Wu, T. Mudge, C. Chakrabarti. E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems. MEMSYS 2015: International Symposium on Memory Systems, Washington DC, October 2015, pp. 60-70.
  • J. Hauswald, Y. Kang, M. Laurenzano, Q. Chen, C. Li, T. Mudge, R. G. Dreslinski, J. Mars, L. Tang. DjiNN and Tonic: DNN as a Service and Its Implications for Future Warehouse Scale Computers. Proc. 42nd Int. Symp. on Computer Architecture (ISCA), Portland, OR, June 2015, pp. 27-40.  [pdf]
  • T. Mudge. Thoughts on Winning the 2014 Eckert-Mauchly Award. IEEE MICRO. May 2015, pp. 144-146.
  • T. Mudge. The Specialization Trend in Computer Hardware—A Perspective. Comm. ACM. Vol. 58, no. 4, April 2015, p. 84.
  •  C. Gao, A. Gutierrez, M. Ranaj, R.G. Dreslinski, T. Mudge, C.-J. Wu. A Study of Mobile Device Utilization.  2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Philadelphia, March 2015, pp. 225-234. [pdf]
  • J. Ballast, M. Ahmed, R.G. Dreslinski, R. Higgins, D-I. Kang, T. Mudge, W. Snapp, E. Van Hensbergen, J. Walters, M. Wollman. The Next-Generation Space Processor (NGSP) Analysis Program: Benchmarking and ARM-Based Heterogeneous Multicore Processor Design for Space Applications. 40th Annual GOMACTech Conference, St. Louis March 2015.
  • J. Hauswald, M. A. Laurenzano, Y. Zhang, C. Li, A. Rovinski, A. Khurana, R.G. Dreslinski, T. Mudge, V. Petrucci, L. Tang, J. Mars.  Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers.  20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Istanbul, March 2015, pp. 223-238. [pdf]
  • Q. Zheng, Y. Chen, H. Lee, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, and T. Mudge. Using Graphics Processing Units in an LTE Base Station. Journal of Signal Processing Systems, vol. 78, no. 1, pp. 35–47, January 2015.

2014

  • S. Jeloka, R. Das, R.G. Dreslinski, T. Mudge, D. Blaauw. “Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration”. The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). [pdf]
  • J. Pusdesris, B. VanderSloot, T. Mudge. “A Memory Rename Table to Reduce Energy and Improve Performance”, 2014 International Symposium on Low Power Electronics Design (ISLPED), August 2014, pp. 279-282. [Poster and text] [pdf]
  • A. Gutierrez, R.G. Dreslinski, T. Mudge. “Evaluating Private vs. Shared Last-Level Caches for Energy Efficiency in Asymmetric Multi-Cores”, Fourteenth International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS), July 2014, pp. 191-198. [pdf]
  • S. Rao, S. Jeloka, R. Das, D. Blaauw, R. Dreslinski, T. Mudge. “VIX: Virtual Input Crossbar for Efficient Switch Allocation”, Fifty first Design Automation Conference (DAC), June 2014, pp. 1-6. [pdf]
  • N. Abeyratne, S. Jeloka, Y. Kang, D. Blaauw, R.G. Dreslinski, R. Das, T. Mudge. “Quality-of-Service for a High-Radix Switch”, Fifty first Design Automation Conference (DAC), June 2014, pp. 1-6. [pdf]
  • J. Hauswald, T. Manville, Q. Zheng, R.G. Dreslinski, C. Chakrabarti, T. Mudge. “A Hybrid Approach to Offloading Mobile Image Classification”, 2014 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2014, pp. 8375-8379. [pdf]
  • R.G. Dreslinski, Q. Zheng, R.P. Higgins, J. Hauswald, D. Blaauw, T. Mudge, C. Chakrabarti, J. Ballast, W. Snapp. “An Architecture for Low-Power High-Performance Embedded Computing”, Thirty ninth Annual GOMACTech Conference (GOMAC), April 2014, pp. 423-426. [pdf]
  • A. Gutierrez, J. Pusdesris, R. Dreslinski, T. Mudge, C. Sudanthi, C.D. Emmons, M. Hayenga, N. Paver. “Sources of Error in Full System Simulation”, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014, pp. 13-22. [Best Paper Award] [pdf]
  • A. Gutierrez, M. Cieslak, B. Giridhar, R. Dreslinski, L. Ceze, T. Mudge. “Integrated 3D-Stacked Server Designs for Increasing Physical Density of Key-Value Stores”, Nineteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2014, pp. 485-498. [pdf]
  • C. Gao, A. Gutierrez, R. G. Dreslinski, T. Mudge, K. Flautner, G. Blake. “A Study of Thread Level Parallelism on Mobile Devices”, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2014, pp. 126-127. [Poster and text] [pdf]

2013

  • B. Giridhar, M. Cieslak, D. Duggal, R. Dreslinski, H. Chen, R. Patti, B. Hold, C. Chakrabarti T. Mudge, D. Blaauw. “Exploring DRAM Organizations for Energy-Efficient and Resilient Exascale Memories”, Proc. of SC 13, Denver, Co, November 2013, 12pp. [pdf]
  • R. G. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, D. Sylvester, D. Blaauw, T. Mudge. “Centip3De: A Many-Core Prototype Exploring 3D Integration and Near-Threshold Computing”, Communications of the ACM (CACM), vol 56, no. 11, November 2013, pp.97-104. [pdf]
  • Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, T. Mudge. “Architecting an LTE Base Station with Graphics Processing Units“, 2013 IEEE Workshop on Signal Processing Systems (SiPS 2013). October 2013, pp .219-224. [pdf]
  • N. Pinckney, R.G. Dreslinski, K. Sewell, D. Fick, T. Mudge, D. Sylvester, D. Blaauw. “Limits of Parallelism and Bossting in Dim Silicon“, IEEE Micro. Sept.Oct 2013, pp. 30-37. [pdf]
  • Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, T. Mudge. “WiBench: An Open Source Kernal Suite for Benchmarking Wireless Systems”, Proc. of the IEEE Int. Symposium on Workload Characterization (IISWC), September 2013, pp.123-132. [pdf]
  • R. Dreslinski, B. Girdihar, M. Cieslak, Y. Kang, D. Blaauw, T. Mudge, J. Vetter, R. Schreiber. “An Evaluation Methodology for Exascale Memory Systems”, Workshop on Modeling & Simulation of Exascale Systems & Applications (MODSIM), Seattle, Wa., September 2013, [pdf]
  • Q. Zheng, Y. Chen, R. Dreslinski, C. Chakrabarti, A. Anastasopoulos, S. Mahlke, T. Mudge. “Parallelization Techniques for Implementing Trellis Algorithms on Graphics Processors”, IEEE International Symposium on Circuits and Systems (ISCAS 2013), May 2013, pp. 1220-1223. [pdf]
  • R. Dreslinski, D. Fick, B. Giridhar, G. Kim, S. SEo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, D. Sylvester, D. Blaauw, T. Mudge. “Centip3De: A 64-Core, 3D Stacked Near-Threshold System”, Micro, IEEE, vol. 33, no.2, pp.8,16, March-April 2013. [pdf]
  • N. Abeyratne, R. Das, Q. Li, K. Sewell, B. Giridhar, R. Dreslinski, D. Blaauw, T. Mudge. “Scaling Toward Kilo-Core Processors with Asymmetric High-Radix Topologies”, 19th IEEE International Symposium on High Performance Computer Architecture (HPCA 2013), February 2013, pp. 496-507. [pdf]
  • D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester. “Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 48, No. 1, January 2013, pp. 104-117. [pdf]

2012

  • A, Sethia, S. Mahlke, G. Dasika, T. Mudge. “A Customized Processor for Energy Efficient Scientific Computing”, IEEE Transactions on Computers, Vol. 61, No.12, December 2012, pp. 1711-1723. [pdf]
  • A. Gutierrez, J. Pusdesris, R. Dreslinski, T. Mudge. “Lazy Cache Invalidation for Self-Modifying Codes”, The International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2012), October 2012, pp. 151-160. [pdf]
  • R. Dreslinski, T. Manville, K. Sewell, R. Das, N. Pinckney, S. Satpathy, D. Blaauw, D. Sylvester, T. Mudge. “XPoint Cache: Scaling Existing Bus Based Coherence Protocols for 2D and 3D Many-Core Systems”, The International Conference on Parallel Architectures and Compilation Techniques (PACT 2012), September 2012, pp. 75-85. [pdf]
  • G. Chen, T. Mudge, D. Sylvester, D. Blaauw. “Centip3De: A 64-Core, 3D Stacked, Near-Threshold System”, Hotchips, August 2012, pp.380-403.[pdf]
  • R. Dreslinski, K. Sewell, S. Satpathy, T. Manville, N. Pinckney, G. Blake, M. Cieslak, R. Das, T. Wenisch, D. Sylvester, D. Blaauw, T. Mudge. “Swizzle Switch: A Self-Arbitrating High-Radix Crossbar for NoC Systems”, Hotchips, August 2012, pp.380 – 403.[pdf]
  • R. Dreslinski, B. Giridhar, N. Pinckney, D. Blaauw, D. Sylvester, T. Mudge. “Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry”, 2012 Workshop on Duplicating, Decontructing and Debunking (WDDD), June 2012, pp. 1-7.[pdf]
  • P. Tandon, J. Chang, R. Dreslinski, P. Ranganathan, T. Mudge, T.F. Wenisch. “PicoServer Revisited: On the Profitability of Eliminating Intermediate Cache Levels”, 2012 Workshop Duplicating, Decontructing and Debunking (WDDD), June 2012, pp. 1-10.[pdf]
  • N. Pinckney, R. Dreslinski, K. Sewell, D. Fick, D. Blaauw, D. Sylvester, T. Mudge. “Limits of Voltage-Scaled Parallel Architectures to Combat Dark Silicon”, 2012 Workshop on Dark Silicon (DaSi), June 2012. [pdf]
  • K. Sewell, R. Dreslinski, T. Manville, S. Satpathy, N. Pinckney, G. Blake, M. Cieslak, R. Das, T. Wenisch, D. Sylvester, D. Blaauw, T. Mudge. “Swizzle-Switch Networks for Many-Core Systems”. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 2, No. 2, June 2012, pp. 278-294. [pdf]
  • S. Satpathy, R. Das, R. Dreslinski, T. Mudge, D. Sylvester, D. Blaauw. “High Radix Self-Arbitrating Switch Fabric with Multiple Arbitration Schemes and Quality of Service”. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012, pp. 406-411. [pdf]
  • S. Seo, R. Dreslinski, M. Woh, Y. Park, C. Charkrabari, S. Mahlke, D. Blaauw, T. Mudge. “Process Variation in Near-Threshold Wide SIMD Architectures”. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012, pp. 980-987. [pdf]
  • N. Pinckney, K. Sewell, R. Dreslinski, D. Fick, T. Mudge, D. Sylvester, and D. Blaauw. “Assessing the Performance Limits of Parallelized Near-Threshold Computing”. Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2012, pp. 1143-1148. [pdf]
  • J. Chang, K. Lim, T. Mudge, P. Ranganathan, D. Roberts, M. Shah. “A Limits Study of Benefits from Nanostore-Based Future Data-Centric System Architectures”. ACM Internation Conference on Computing Frontiers (CF’ 12), May 2012, pp. 33-42. [pdf]
  • D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, D. Blaauw. “Centip3De: A 3930 DMIPS/W Configurable Near‐Threshold 3D Stacked System With 64 ARM Cortex‐M3 Cores”, IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, February 2012, pp. 190-191. [pdf]
  • S. Satpathy, K. Sewell, T. Manville, Yen-Po Chen, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw. “A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least recently granted priority and quality of service arbitration in 45nm CMOS”, IEEE International Solid-State Circuits Conference (ISSCC). San Francisco, CA, February 2012, pp. 478-479. [pdf]

2011

  • A. Gutierrez, R. Dreslinski, A. Saidi, C. Emmons, N. Paver. T. Wenisch, T. Mudge. “Full-System Analysis and Characterization of Interactive Smartphone Applications”, IEEE International Symposium on Workload Characterization (IISWC-2011), Austin, TX, USA, November 6-8, 2011. pp. 81-90. [pdf]
  • G. Dasika, A. Sethia, T. Mudge, S. Mahlke. “PEPSC: A Power-Efficient Processor for Scientific Computing”, 20th Int. Conf. on Parallel Architectures and Compilation Techniques (PACT) Galveston Island, Texas, October 2011, pp. 101-110. [pdf]
  • C. Yang, Y. Emre, C. Chakrabarti, and T.Mudge, “Flexible product code-based ECC schemes for MLC Nand FLASH memories”, IEEE Workshop on Signal Processing Systems, (SiPS 2011), October 4-7 2011, Beirut, Lebanon. [pdf]
  • S. Satpathy, R. Dreslinski, T. Ou, D. Sylvester, T. Mudge, D. Blaauw. “SWIFT: A 2.1Tb/s 32×32 Self-Arbitrating Manycore Interconnect Fabric”, Symposia on VLSI Technology and Circuits. Kyoto, Japan, June 2011, pp. 138-139. [Winner in the 11th Annual International VLSI Symposium Low Power Contest] [pdf]
  • D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wiekowski, G. Chen, T. Mudge, D. Sylvester, and D. Blaauw. “Design and Implementation of Centip3De, a 7-layer Many-Core System”, Proc. of the ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 2011. [Winner DAC/ISSCC Student Design Contest]
  • M. Woh, S. Satpathy, R. Dreslinski, D. Kershaw, D. Sylvester, D. Blaauw, T. Mudge. “Low Power Interconnects for SIMD Computers”, Proceedings Design, Automation and Test in Europe DATE 11. March 2011. Grenoble, France. pp. 600-605. [pdf]
  • A. Hormati, M. Samadi, M. Woh, T. Mudge, S. Mahlke. “Sponge: Portable Stream Programming on Graphics Engines”, 16th International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS XVI. March 2011, Newport Beach, CA. pp. 381-392. [pdf]
  • G. Blake, R. Dreslinski, T. Mudge. “Bloom Filter Guided Transaction Scheduling”, Proceedings 37th International Symposium on High Performance Computer Architecture HPCA 17. February 2011. San Antonio, TX. pp. 75-86. [pdf]

2010

  • M. Woh, S. Seo, C. Chakrabarti, S. Mahlke, T. Mudge. “An Ultra Low Power SIMD Processor for Wireless Communications”, Proceedings of the Asilomar Conference on Signals, Systems and Computers. November, 2010. Asilomar, CA. [pdf]
  • G. Chen, D. Sylvester, D. Blaauw, T. Mudge. “Yield-driven Near-threshold SRAM Design”, IEEE Transactions on VLSI Systems. vol 18, no 11. November, 2010. pp. 1590-1598. [pdf]
  • G. Dasika, M. Woh, S. Seo, N. Clark, T. Mudge, S. Mahlke. “Mighty-Morphing Power-SIMD”, Proceedings 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems CASES 10. October, 2010. Scottsdale, AZ. pp. 67-75. [pdf]
  • G. Dasika, A. Sethia, V. Robby, T. Mudge, S. Mahlke. “MEDICS: Ultra-Portable Processing for Medical Image Reconstruction”, 19th International Conference on Parallel Architectures and Compilation Techniques PACT 10. September, 2010. Vienna, Austria. pp. 181-192. [pdf]
  • H. Lee, C. Chakrabarti, T. Mudge. “A Low Power DSP for Wireless Communications”, IEEE Transactions on VLSI Systems. vol 18, no 9. September, 2010. pp. 1310-1322. [pdf]
  • S. Seo, M. Woh, R. Dreslinski, C. Chakrabarti, S. Mahlke, T. Mudge. “Diet SODA: A Power-Efficient Processor for Digital Cameras”,International Symposium on Low Power Electronics and Design ISLPED. August, 2010. pp. 79-84. [pdf]
  • T. Mudge. “Challenges And Opportunities For Extremely Energy-efficient Processors”, IEEE MICRO. vol 30, no 4. July, 2010. pp. 20-22.[pdf]
  • G. Blake, R. Dreslinski, T. Mudge, K. Flautner. “Evolution of Thread-Level Parallelism in Desktop Applications”, The 37th International Symposium on Computer Architecture. June, 2010. St. Malo, France. pp. 302-313. [pdf]
  • M. Shah, P. Ranganathan, J. Chang, N. Tolia, D. Roberts, T. Mudge. “Data Dwarfs: Motivating a Coverage Set for Future Large Data Center Workloads”, Architectural Concerns in Large Datacenters Workshop held in conjunction with The 37th International Symposium on Computer Architecture. June, 2010. St. Malo, France. [Poster and text] [pdf]
  • S. Satpathy, Z. Foo, B. Giridhar, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw. “A 1.07 Tbit/s 128×128 Swizzle Network for SIMD Processors”, IEEE Symposium on VLSI Circuits. June, 2010. Honolulu, Hawaii. pp. 81-82. [pdf]
  • M. Wieckowski, R. Dreslinski, T. Mudge, D. Blaauw, D. Sylvester. “Circuit design advances for ultra-low power sensing platforms”, Proceedings of SPIE. vol 7679, 76790W. April, 2010. pp. 1-7. DOI: 10.1117/12.850720. [pdf]
  • K. Lim, J. Chang, J. Santos, Y. Turner, T. Mudge, P. Ranganathan, S. Reinhardt, T. Wenisch. “Hypervisor-based Prototyping of Disaggregated Memory and Benefits of VM Consolidation”, 15th International Conference Architectural Support for Programming Languages and Operating Systems. March, 2010. Pittsburgh, Pennsylvania. [Poster] [pdf]
  • A. Hormati, Y. Choi, M. Woh, M. Kudlur, R. Rabbah, T. Mudge, S. Mahlke. “MacroSS: Macro-SIMDization of Streaming Applications”, 15th International Conference on Architectural Support for Programming Languages and Operating Systems. March, 2010. Pittsburgh, Pennsylvania. pp. 285-296. [pdf]
  • R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge. “Near-threshold Computing: Reclaiming Moore’s Law Through Energy Efficient Integrated Circuits”, Proceedings of the IEEE. vol 98, no 2. February, 2010. pp. 253-256. [pdf]
  • M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. “AnySP: Anytime Anywhere Anyway Signal Processing”, IEEE MICRO Top Picks Issue. vol 30, no 1. January, 2010. pp. 81-91. [Top Pick: selected as one of the 12 best papers in computer architecture for 2009] [pdf]
  • T. Mudge. “Guest Editor’s Introduction: Top Picks From The Computer Architecture Conferences Of 2009”, IEEE MICRO. vol 30, no 1. January, 2010. pp. 8-11. [pdf]
  • M. Woh, S. Mahlke, T. Mudge, C. Chakrabarti. “Mobile Supercomputers for the Next-Generation Cell Phone”, Computer. vol 43, no 1. January, 2010. pp. 93-97. [pdf]
  • T. Kgil, D. Roberts, T. Mudge. (Eds.) Y. Xie, J. Cong, S. Sapatnekar. “PicoServer: Using 3D Stacking Technology To Build Energy Efficient Servers”, Kluwer Hardcover. 2010. pp. 219-260. ISBN: 978-1-4419-0783-7. [pdf]

2009

  • G. Dasika, A. Sethia, T. Mudge, S. Mahlke. “Low Power Scientific Computing”, 2009 Workshop on New Directions in Computer Architecture held in conjunction with The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December, 2009. New York, New York. pp. 7-8. [pdf]
  • G. Blake, R. Dreslinski, T. Mudge. “Proactive Transaction Scheduling for Contention Management”. The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December, 2009. New York, New York. pp. 156-167. [pdf]
  • R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge. “Overcoming Moore’s Curse: Techniques for Powering Large Transistor Counts in Sub-Micron Technologies”, 2009 Workshop on New Directions in Computer Architecture held in conjunction with The 42nd Annual IEEE/ACM International Symposium on Microarchitecture. December, 2009. New York, New York. pp. 20-21. [pdf]
  • Y. Lin, M. Woh, S. Seo, C. Chakrabarti, S. Mahlke, T. Mudge. “Baseband Processing Architectures for SDR”, CRC Press. Chapter 21 in Wireless, Networking, Radar, Sensor Array Processing and Nonlinear Signal Processing, The Digital Signal Processing Handbook. November, 2009. pp. 21-1 — 21-18. [pdf]
  • G. Blake, R. Dreslinski, T. Mudge. “A Survey of Multicore Processors”, IEEE Signal Processing Magazine. vol 26, no 6. November, 2009. pp. 26-37. [pdf]
  • A. Hormati, Y. Choi, M. Kudlur, R. Rabbah, T. Mudge, S. Mahlke. “Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures”, Parallel Architectures and Compilation Techniques. September, 2009. pp. 214-223. [pdf]
  • M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge. “Analyzing the Next Generation Software Defined Radio for Architectures”, Springer Journal of Signal Processing Systems. August, 2009. New York. DOI: 10.1007/s11265-009-0402-z. [published online] [pdf]
  • S. Seo, M. Woh, S. Mahlke, T. Mudge, S. Vijay, C. Chakrabarti. “Customizing Wide-SIMD Architectures for H.264”, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. July, 2009. Greece. pp. 172-179. [pdf]
  • R. Dreslinski, D. Fick, D. Blaauw, D. Sylvester, T. Mudge. “Reconfigurable Multicore Server Processors for Low Power Operation”, International Workshop on Systems, Architectures, Modeling, and Simulation. July, 2009. Greece. pp. 247-254. [pdf]
  • K. Lim, J. Chang, T. Mudge, P. Ranganathan, S. Reinhardt, T. Wenisch. “Disaggregated Memory for Expansion and Sharing in Blade Servers”, The 36th International Symposium on Computer Architecture. June, 2009. Austin, Texas. pp. 267-278. [pdf]
  • A. Saidi, N. Binkert, S. Reinhardt, T. Mudge. “End-To-End Performance Forecasting: Finding Bottlenecks Before They Happen”, The 36th International Symposium on Computer Architecture. June, 2009. Austin, Texas. pp. 361-370. [pdf]
  • M. Woh, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. “AnySP: Anytime Anywhere Anyway Signal Processing”, The 36th International Symposium on Computer Architecture. June, 2009. Austin, Texas. pp. 128-139. [pdf]
  • R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge. “Near Threshold Computing: Overcoming Performance Degradation from Aggressive Voltage Scaling”, Workshop on Energy-Efficient Design held in conjunction with The 36th International Symposium on Computer Architecture WEED. June, 2009. Austin, Texas. pp. 44-49. [pdf]
  • Ringenberg J., T. Mudge. “SuiteSpecks and SuiteSpots: A Methodology for the Automatic Conversion of Benchmarking Programs into Intrinsically Checkpointed Assembly Code”, 2009 IEEE International Symposium on Performance Analysis of Systems and Software. April, 2009. Boston, Massachusetts. pp. 227-237. [pdf]
  • D. Roberts, T. Kgil and T. Mudge, “Integrating NAND Flash Devices Onto Servers”, Communications of the ACM, Research Highlights. vol 52, no 4. April, 2009. pp. 98-103. [pdf]
  • D. Roberts, T. Kgil, T. Mudge. “Using Non-Volatile Memory to Save Energy in Servers”. Design, Automation and Test in Europe. April, 2009. Nice, France. pp. 743-748. [pdf]
  • Y. Choi, Y. Lin, N. Chong, S. Mahlke, T. Mudge. “Stream Compilation for Real-time Embedded Multicore Systems”, The 2009 International Symposium on Code Generation and Optimization. March, 2009. pp. 210-220. [pdf]
  • K. Sewell, T. Mudge, S. Reinhardt. “EXtreme Virtual Pipelining (XVP): Moving Towards Scalable Multithreaded Processors”, Wild and Crazy Ideas held in conjunction with 16th International Conference on Architectural Support for Programming Languages and Operating Systems. March, 2009. Washington DC. [pdf]
  • K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt. “Server Designs for Warehouse Computing Environments”, IEEE MICRO. vol 29, no 1. January, 2009. pp. 41-49. [pdf]

2008

  • M. Woh, Y. Lin, S. Seo, S. Mahlke, T. Mudge, C. Chakrabarti, R. Bruce, D. Kershaw, A. Reid, M. Wilder, K. Flautner. “From SODA to Scotch: The Evolution of a Wireless Baseband Processor”, November, 2008. Lake Como. pp. 152-163. [Best Paper] [pdf]
  • R. Dreslinski, G. Chen, T. Mudge, D. Blaauw, D. Sylvester, K. Flautner. “Reconfigurable Energy Efficient Near Threshold Cache Architectures”, The 41st IEEE/ACM International Symposium on Microarchitecture. November, 2008. Lake Como, Italy. pp. 459-470. [pdf]
  • T. Kgil, A. Saidi, N. Binkert, S. Reinhardt, K. Flautner, T. Mudge. “PicoServer: Using 3D Stacking Technology To Build Energy Efficient Servers”, ACM Journal on Emerging Technologies in Computing Systems. vol 4, no 4. October, 2008. 33 pp. [pdf]
  • Y. Lin, Y. Choi, S. Mahke, T. Mudge, C. Chakrabarti. “A parameterized dataflow language extension for embedded streaming systems”, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. July, 2008. Samos, Greece. pp. 10-17. [pdf]
  • E. Ozer, R. Dreslinski, T. Mudge, S. Biles, K. Flautner. (Eds.) M. Berekovic, N. Dimopoulos, S. Wong. “Energy-efficient simultaneous thread fetch from different cache levels in a soft real-time SMT processor”, Springer-Verlag Berlin Heidelberg. SAMOS VIII Workshop. July, 2008. Greece. pp. 12-22. [pdf]
  • T. Kgil, D. Roberts, T. Mudge. “Improving NAND Flash based disk caches”, The 35th International Symposium on Computer Architecture. June, 2008. Beijing, China. pp. 327-338. [pdf]
  • K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, S. Reinhardt. “Understanding and designing new server architectures for emerging warehouse-computing environments”, The 35th International Symposium on Computer Architecture. June, 2008. Beijing, China. pp. 315-326. [Top Pick: selected as one of the 12 best papers in computer architecture for 2008] [pdf]
  • A. Saidi, N. Binkert, T. N. Mudge, S. K. Reinhardt. “Full System Critical Path Analysis”, 2008 IEEE International Symposium on Performance Analysis of Systems and Software. April, 2008. pp. 63-74. [pdf]
  • D. Roberts, N. S. Kim, T. Mudge. “On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology”, Journal on Microprocessors and Microsystems. vol 32. April 2008. pp. 244-253. [pdf]
  • M. Woh, Y. Lin, S. Seo, T. Mudge, S. Mahlke. “Analyzing the scalability of SIMD for the next generation software defined radio”, 33rd International Conference on Acoustics, Speech, and Signal Processing. April, 2008. Las Vegas, Nevada. pp. 5388-5391. [pdf]
  • D. B. C. Tokunaga, T. Mudge. “True Random Number Generator with a Metastability-based Quality Control”, IEEE Journal on Solid-State Circuits. vol 43, no 1. January, 2008. pp. 78-85. [pdf]
  • S. Das, D. Roberts, D. Blaauw, D. Bull, T. Mudge. (Eds.) A. Wang, S. Naffziger. “Architectural Techniques For Adaptive Computing”, Springer Science+Business Media. Adaptive Techniques for Dynamic Processor Optimization. 2008. pp. 175-204. [pdf]

2007

  • G. Chen, D. Blaauw, T. Mudge, D. Sylvester, N. Kim. “Yield-Driven Near-Threshold SRAM Design”, IEEE/ACM International Conference on Computer Aided Design. November, 2007. pp. 660-666. [pdf]
  • Y. Lin, M. Kudlur, S. Mahlke, T. Mudge. “Hierarchical Coarse-grained Stream Compilation for Software Defined Radio”, International Conference on Compiler and Architecture Support for Embedded Systems. October, 2007. Salzburg, Austria. pp. 115-124. [pdf]
  • S. Seo, T. Mudge, Y. Zhu, C. Chakrabarti. “Design and Analysis of LDPC Decoders for Software Defined Radio”, 2007 IEEE Workshop on Signal Processing Systems. October, 2007. Shanghai, China. pp. 210-215. [pdf]
  • R. Dreslinski, B. Zhai, T. Mudge, D. Blaauw, D. Sylvester. “An Energy Efficient Parallel Architecture Using Near Threshold Operation”, 16th International Conference on Parallel Architectures and Compilation Techniques. September, 2007. Romania. pp. 175-188. [pdf]
  • D. Roberts, R. Dreslinski, E. Karl, T. Mudge, D. Sylvester, D. Blaauw. “When Homogeneous becomes Heterogeneous: Wearout Aware Task Scheduling for Streaming Applications”, Workshop on Operating System Support for Heterogeneous Multicore Architectures. September, 2007. Romania. pp. 5-13. [pdf]
  • B. Zhai, R. Dreslinski, D. Blaauw, T. Mudge, D. Sylvester. “Energy Efficient Near-threshold Chip Multi-processing”, International Symposium on Low Power Electronics and Design – 2007. August, 2007. pp. 32-37. [Best Paper Nomination] [pdf]
  • D. Roberts, N. S. Kim, T. Mudge. “On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology”, 10th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. August, 2007. Lubeck, Germany. pp. 570-578. [pdf]
  • M. Woh, S. Seo, H. Lee, Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. (Eds.) S. Vassiliadis et al. Springer-Verlag Berlin Heidelberg. “The Next Generation Challenge for Software Defined Radio”, SAMOS VII Workshop. July, 2007. Greece. pp. 343-354. [Best Paper] [pdf]
  • G. Blake, T. Mudge. “Duplicating and Verifying LogTM with OS Support in the M5 Simulator”, Workshop on Duplicating, Deconstructing, and Debunking held in conjunction with the International 34th Symposium on Computer Architecture. June, 2007. San Diego, California. pp. 23-31. [pdf]
  • R. Dreslinski, A. Saidi, T. Mudge, S. Reinhardt. “Analysis of hardware prefetching across virtual page boundaries”, ACM International Conference on Computing Frontiers. May, 2007. Italy. pp. 13-22. [pdf]
  • C. Tokunaga, D. Blaauw, T. Mudge. “True random number generator with a metastable-based quality control”, International Solid-State Circuits Conference. February, 2007. pp. 404-405. [pdf]
  • Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. “SODA: A High-Performance DSP Architecture for Software-Defined Radio”, IEEE MICRO Top Picks Issue. January, 2007. pp. 114-123. [pdf]

2006

  • Y. Lin, R. Mullenix, M. Woh, S. Mahlke, T. Mudge, A. Reid, K. Flautner. “SPEX: A programming language for software defined radio”, 2006 SDR Technical Conference. November, 2006. Orlando, Florida. Section 2.3, 6 pp. [pdf]
  • Kgil T., D’Souza, S., A. Saidi, N. Binkert, R. Dreslinski, S. Reinhardt, K. Flautner, T. Mudge. “PicoServer: Using 3D stacking technology to enable a compact energy efficient chip multiprocessor”, 12th International Conference on Architectural Support for Programming Languages and Operating Systems. November, 2006. pp. 117-128. [pdf]
  • T. Kgil, T. Mudge. “FlashCache: A NAND Flash memory file cache for low power web servers”, Conference for Compiler and Architecture Support for Embedded Systems. October, 2006. Seoul, South Korea. pp. 103-112. [pdf]
  • H. Lee, C. Chakrabati, T. Mudge. “Reducing idle mode power in software defined radio terminals”, International Symposium on Low Power Electronics and Design – 2006. October, 2006. Tegernsee, Germany. pp. 101-106. [pdf]
  • Y. Lin, S. Mahlke, T. Mudge, C. Chakrabarti, A. Reid, K. Flautner. “Design and implementation of Turbo decoders for software defined radio”, IEEE 2006 Workshop on Signal Processing Systems. October, 2006. Banff, Canada. pp. 22-27. [pdf]
  • E. Karl, D. Sylvester, D. Blaauw, T. Mudge. “Reliability modeling and management in dynamic microprocessor-based systems”, The ACM/IEEE Design Automation Conference. June, 2006. San Francisco, California. pp. 1057-1060. [pdf]
  • S. Plaza, I. Kountanis, Z. Andraus, V. Bertacco, T. Mudge. “Advances and insights into parallel SAT solving”, International Workshop on Logic and Synthesis. June, 2006. pp. 188-194. [pdf]
  • Y. Lin, H. Lee, M. Woh, Y. Harel, S. Mahlke, T. Mudge, C. Chakrabarti, K. Flautner. “SODA: A low-power architecture for software radio”, 33rd Annual International Symposium on Computer Architecture. June, 2006. Boston, Massachusetts, USA. pp. 89-101. [Top Pick: selected as one of the 12 best papers in computer architecture for 2006] [pdf]
  • S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, T. Mudge, K. Flautner. “A self-tuning dynamic voltage scaled processor using delay-error detection and correction”, IEEE International Conference on Integrated Circuit Design and Technology. May, 2006. Padova, Italy. pp. 211-214. [pdf]
  • A. Jerraya, T. Mudge. “Guest editorial: Concurrent hardware and software design for multiprocessor SoC”, ACM Transactions on Embedded Computing Systems. vol 5, no 2. May, 2006. pp. 259-262.
  • S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, T. Mudge. “A self-tuning DVS processor using delay-error detection and correction”, IEEE Journal on Solid-State Circuits. vol 41, no 4. April, 2006. pp. 792-804. [pdf]

2005

  • H. Lee, Y. Lin, Y. Harel, M. Woh, S. Mahlke, T. Mudge, K. Flautner. “Software defined radio-A high performance embedded challenge”, 1st International Conference on High Performance Embedded Architectures and Compilers. November, 2005. Barcelona, Spain. [pdf]
  • D. Oehmke, N. Binkert, T. Mudge, S. Reinhardt. “How to fake 1000 registers”, 38th Annual IEEE/ACM Symposium Microarchitecture. November, 2005. pp. 7-18. [Best Paper Nomination] [pdf]
  • Y. Lin, H. Lee, Y. Harel, M. Woh, N. Baron, S. Mahlke, T. Mudge, K. Flautner. “A system solution for high-performance, low-power SDR”, Proc. 2005 SDR Technical Conf. November, 2005. Annaheim, California. [pdf]
  • N. S. Kim, T. Kgil, K. Bowman, V. De, T. Mudge. “Total power-optimal pipelining and parallel processing under process variations in nanometer technology”, International Conference of Computer Aided Design ICCAD. November, 2005. pp. 535-540. [pdf]
  • N.S. Kim, D. Blaauw and T. Mudge, “Quantitative analysis and optimization techniques for on-chip cache leakage power”, IEEE Transactions on VLSI. vol 13, no 10. October, 2005. pp. 1147-1156. [pdf]
  • H. Lee, T. Mudge. “A dual processor solution for the MAC layer of a software defined radio terminal”, Conference on Compiler and Architecture Support for Embedded Systems. September, 2005. California. pp. 257-265. [pdf]
  • T. Mudge.“Introduction to the special issue of the IEEE Transactions in Computers on Energy Efficient Computing”, IEEE Transactions in Computers on Energy Efficient Computing. vol 54, no 6. June, 2005. pp. 641-641. [pdf]
  • W. Shi, H. H. Lee, G. Gu, M. Ghosh, L. Falk, T. Mudge. “An Intrusion tolerant and self-recoverable network service system using security enhanced chip multiprocessors”, The 2nd International Conference on Autonomic Computing. June, 2005. Seattle, Washington. [pdf]
  • S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw, T. Austin, T. Mudge, K. Flautner. “A self-tuning DVS processor using delay-error detection and correction”, 2005 Symposium on VLSI Circuits. June, 2005. Kyoto, Japan. pp. 258-261. [pdf]
  • A. Cheng, G. Tyson, T. Mudge. “PowerFITS: Reduce Dynamic and Static I-cache power using application specific instruction set synthesis”, The IEEE International Symposium on Performance Analysis of Systems and Software. March, 2005. Austin, Texas. pp. 32-41. [pdf]
  • R. Bai, N. S. Kim, T. Mudge, D. Sylvester. “Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage”, Design, Automation and Test in Europe. March, 2005. Munich, Germany. pp. 650-651. [pdf]
  • D. Roberts, T. Austin, D. Blaauw, T. Mudge. “Error analysis for the support of robust voltage scaling”,6th International Symposium on Quality Electronic Design. March, 2005. pp. 65-70. [pdf]
  • J. Ringenberg, C. Pelosi, D. Oehmke, T. Mudge. “Intrinsic checkpointing: A methodology for decreasing simulation time through binary modification”, IEEE International Symposium on Performance Analysis of Systems and Software. March, 2005. Austin, Texas. pp. 78-88. [pdf]
  • R. Bai, N. S. Kim, D. Sylvester, T. Mudge. “Total leakage optimization strategies for multi-level caches”, ACM/IEEE Great Lakes Symposium on VLSI. 2005. pp. 381-384. [pdf]
  • H. Kaul, D. Sylvester, D. Blaauw, T. Mudge, T. Austin. “DVS for on-chip bus designs based on timing error correction”, Design, Automation and Test in Europe. 2005. Munich, Germany. pp. 80-85. [pdf]
  • T. Austin, V. Bertacco, D. Blaauw, T. Mudge. “Opportunities and challenges for better than worst-case design”, Asia South Pacific Design Automation Conference. vol 1. January, 2005. China. pp. I/2-I/7. [pdf]

2004-2000

  • D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, K. Flautner. “Razor: circuit-level correction of timing errors for low-power operation”, IEEE MICRO. vol 24, no 6. November, 2004. pp. 10-20. [Best Paper, Top Pick: selected as one of the best papers in computer architecture for 2006 from the top conferences of 2003/4: Micro-36, HPCA 10, ISCA 31, PACT 2004, ASPLOS XI] [pdf]
  • T. Kgil, L. Falk, T. Mudge. “ChipLock: Support for Secure Microarchitectures”, Workshop on Architectural Support for Security and Anti-virus held in conjunction with the 11th International Conferference on Architectural Support for Programming Languages and Operating Systems. October, 2004. Boston, Massachusetts. pp. 130-139. [pdf]
  • Y. Lin, N. Baron, H. Lee, S. Mahlke, T. Mudge. “A programmable vector coprocessor architecture for wireless applications”, 3rd Workshop on Application Specific Processors held in conjunction with the International Conference on Hardware/Software Codesign and System Synthesis. September, 2004. Stockholm. pp. 103-110. [pdf]
  • N. Kim, T. Kgil, V. Bertacco, T. Austin, T. Mudge. “Microarchitectural power modeling techniques for deep sub-micron microprocessors”, The International Symposium on Low Power Electronics and Design. August, 2004. Newport Beach, California. pp. 212-217. [pdf]
  • N. Kim, K. Flautner, D. Blaauw, T. Mudge.“Single Vdd and single Vt super-drowsy techniques for low-leakage high-performance instruction caches”, The International Symposium on Low Power Electronics and Design. August, 2004. Newport Beach, California. pp. 54-57. [pdf]
  • S. Lee, T. Austin, D. Blaauw, T. Mudge. “Reducing pipeline energy demands with local DVS and dynamic retiming”, The International Symposium on Low Power Electronics and Design. August, 2004. Newport Beach, California. pp. 319-324. [pdf]
  • A. Cheng, G. Tyson, T. Mudge. “FITS: Framework-based instruction-set tuning synthesis for embedded application specific processors”, The ACM/IEEE Design Automation Conference. June, 2004. San Diego, California. pp. 920-923. [pdf]
  • S. Lee, S. Das, V. Bertacco, T. Austin, D. Blaauw, T. Mudge. “Circuit-aware architectural simulation”, The ACM/IEEE Design Automation Conference. June, 2004. San Diego, California. pp. 305-310. [pdf]
  • T. Austin, D. Blaauw, S. Mahlke, T. Mudge, C. Chakrabati, W. Wolf. “Mobile Supercomputers”, Computer. vol 37, no 5. May, 2004. pp. 81-83. [pdf]
  • A. Cheng, G. Tyson, T. Mudge. “FITS: Increasing code density for embedded systems with a cost-effective 16-bit ISA synthesis technique” 2nd IEEE/ACM Workshop on Optimizations for DSP and Embedded Systems held in conjunction with the International Symposium on Code Generation and Optimization”, March, 2004. San Jose, California.
  • N. Kim, K. Flautner, D. Blaauw, T. Mudge. “Circuit and microarchitectural techniques for reducing cache leakage power”, IEEE Transactions on VLSI. vol 12, no 2. February, 2004. pp. 167-184. [pdf]
  • T. Austin, D. Blaauw, T. Mudge, K. Flautner. “Making Typical Silicon Matter with Razor”, Computer. vol 37, no 3. 2004. pp. 57-65. [pdf]
  • D. Ernst, N. Kim, S. Das, S. Pant, T. Pham, R. Rao, C. Ziesler, D. Blaauw, T. Austin, T. Mudge, K. Flautner. “Razor: A low-power pipeline based on circuit-level timing speculation”, The 36th Annual IEEE/ACM Symposium on Microarchitecture. December, 2003. pp. 7-18. [Best paper] [pdf]
  • J. Ringenberg, D. Oehmke, T. Austin, T. Mudge. “SimpleDSP: A Fast and Flexible DSP Processor Model”, 5th Workshop on Media and Streaming Processors held in conjunction with the 36th Annual IEEE/ACM Symposium on Microarchitecture. December, 2003. [pdf]
  • N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, N. Vijaykrishnan. “Leakage Current: Moore’s Law Meets Static Power”, Computer. vol 36, no 12. December, 2003. pp. 68-75. [pdf]
  • N. Kim, D. Blaauw, T. Mudge. “Leakage power optimization techniques for ultra deep sub-micron multi-level caches”, International Conference of Computer Aided Design. November, 2003. San Jose, California. pp. 627-632. [pdf]
  • N. Kim, T. Mudge, R. Brown. “A 2.3Gb/s fully integrated and synthesizable AES Rijndael core” IEEE Custom Integrated Circuits Conference. September, 2003. pp. 193-196. [pdf]
  • N. Kim, T. Mudge. “Microarchitecture for a low power register file with reduced register ports”, The International Symposium on Low Power Electronics and Design. August, 2003. Seoul, South Korea. pp. 384-389. [pdf]
  • N. Kim, T. Mudge. “Reducing register ports using delayed write-back queues and operand pre-fetch”, International Supercomputing Conference. June, 2003. San Francisco, California. pp. 172-182. [pdf]
  • G. Gao, T. Mudge.“Special Issue on Compilers, Architecture, and Synthesis for Embedded Systems”, ACM Transactions on Embedded Computer Systems. vol 2, no 2. 2003.
  • K. Flautner, T. Mudge. “Vertigo: Automatic performance-setting for Linux”, The 5th Operating Systems Design and Implementation. December, 2002. pp. 105-116. [pdf]
  • S. Martin, K. Flautner, D. Blaauw, T. Mudge. “Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads”, International Conference of Computer Aided Design. November, 2002. San Jose, California. pp. 721-725. [ICCAD Ten Year Retrospective Most Infulential Paper Award][pdf]
  • N. Kim, K. Flautner, D. Blaauw, T. Mudge. “Drowsy instruction caches: Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction”, 35th Annual IEEE/ACM Symposium on Microarchitecture. November, 2002. pp. 219-230. [pdf]
  • K. Flautner, S. Reinhardt, T. Mudge. “Automatic performance setting for dynamic voltage scaling”, ACM Journal on Wireless Networks. vol 8, no 5. September, 2002. pp. 507-520. [pdf]
  • N. Kim, T. Austin, T. Mudge. “Low-energy data cache using sign compression and cache line bisection”, 2nd Annual Workshop on Memory Performance Issues held in conjunction with the 29th Annual International Symposium on Computer Architecture. May, 2002. Anchorage, Alaska. [pdf]
  • K. Flautner, N. Kim, S. Martin, D. Blaauw, T. Mudge.“Drowsy Caches: Simple techniques for reducing leakage power”, The 29th Annual International Symposium on Computer Architecture. May, 2002. Anchorage, Alaska. pp. 148-157. [pdf]
  • D. Blaauw, S. Martin, T. Mudge, K. Flautner. “Leakage current reduction in VLSI systems”, Journal of Circuits, Systems, and Computers. vol 11, no 6. 2002. pp. 621-636.
  • M. Guthaus, J. Ringenberg, D. Ernst, T. Austin, T. Mudge, R. Brown. “MiBench: A free, commercially representative embedded benchmark suite”, IEEE 4th Annual Workshop on Workload Characterization, held in conjunction with The 34th Annual IEEE/ACM Symposium on Microarchitecture. December, 2001. Austin, Texas. pp. 3-14. [pdf]
  • V. Cuppu, B. Jacob, B. Davis, T. Mudge. “High-performance DRAMs in workstation environments”, IEEE Transactions on Computers. vol 50, no 11. November, 2001. pp. 1133-1153. [pdf]
  • K. Flautner, S. Reinhardt, T. Mudge. “Automatic performance setting for dynamic voltage scaling”, 7th Annual International Conference On Mobile Computing and Networking. July, 2001. Rome, Italy. pp. 260-271. [pdf]
  • A. Eden, J. Ringenberg, S. Sparrow, T. Mudge. “Hybrid myths in branch prediction”, 5th World Multiconference on Systemics, Cybernetics and Informatics and the 7th Interenational Conference on Information Systems Analysis and Synthesis. vol XIV. July, 2001. Orlando, Florida. pp. XIV 74-81. [pdf]
  • M. Postiff, D. Greene, S. Raasch, T. Mudge. “Integrating superscalar processor components to implement register caching”, 15th ACM International Conference On Supercomputing. June, 2001. Sorrento, Italy. pp. 348-357. [pdf]
  • B. Jacob, T. Mudge, “Uniprocessor virtual memory without TLBs”, IEEE Transactions on Computers. vol 50, no 5. May, 2001. pp. 482-499. [pdf]
  • T. Mudge. “Power: A first class design constraint”, Computer. vol 34, no 4. April, 2001. pp. 52-57. [pdf]
  • N. Kim, T. Austin, T. Mudge, D. Grunwald. (Eds.) R. Melhem, R. Graybill. “Challenges for architectural level power modeling”, Kluwer Academic Publishers. Power Aware Computing. 2001. [pdf]
  • M. Postiff, D. Greene, T. Mudge. “The store-load address table and speculative register promotion”, 33rd Annual IEEE/ACM Symposium Microarchitecture. December, 2000. pp. 235-244. [pdf]
  • T. Mudge. “Power: A first class design constraint for future architectures”, 7th International Conference on High Performance Computing. December, 2000. Bangalore, India. pp. 215-224.
  • D. Van Campenhout, T. Mudge, J. P. Hayes. “Collection and analysis of microprocessor design errors”, IEEE Design and Test. vol 17, no 4. October, 2000. pp. 51-60. [pdf]
  • B. Davis, B. Jacob, T. Mudge. “The new DRAM interfaces: SDRAM, RDRAM and variants”, 3rd International Symposium on High Performance Computing. October, 2000. Tokyo, Japan. pp. 26-31. [pdf]
  • K. Flautner, S. Reinhardt, T. Mudge.“Thread-level parallelism and interactive performance of desktop applications”, 9th International Conference on Architectural Support for Programming Languages and Operating Systems. August, 2000. pp. 129-138. [pdf]
  • B. Davis, T. Mudge, B. Jacob. “DDR2 and low latency variants”, Memory Wall Workshop held in conjunction with the 26th Annual International Symposium on Computer Architecture. June, 2000. [pdf]
  • A. Eden, B. Joh, T. Mudge. “Web latency reduction via client-side prefetching”, 2000 IEEE International Symposium on Performance Analysis of Systems and Software. April, 2000. Austin, Texas. pp. 193-200. [pdf]
  • K. Flautner, R. Uhlig, S. Reinhardt, T. Mudge. “Thread level parallelism of desktop applications”, Workshop on Multi-threaded Execution, Architecture and Compilation held in conjunction with the 6th International Symposium on High Performance Computer Architecture. January, 2000. Toulouse.
  • C. Lefurgy, E. Piccininni, T. Mudge. “Reducing code size with run-time decompression”, The 6th International Symposium on High-Performance Computer Architecture. January, 2000. pp. 218-227. [pdf]

1999-1995

  • C. Lefurgy, E. Piccininni, T. Mudge. “Evaluation of a high performance code compression method”, The 32nd Annual Symposium on Microarchitecture. November, 1999. pp. 93-102. [pdf]
  • D. Van Campenhout, T. Mudge, J. P. Hayes. “Error simulation with conditional error models”, 4th IEEE International High Level Design Validation and Test Workshop. November, 1999. La Jolla, California. pp. 198-205. [pdf]
  • C. Lefurgy, T. Mudge. “Fast software-managed code decompression”, 2nd International Workshop on Compiler and Architecture Support for Embedded Systems. October, 1999. pp. 139-143. [pdf]
  • M. Postiff, G. Tyson, T. Mudge. “Performance limits of trace caches”, Journal of Instruction Level Parallelism. October, 1999. [pdf]
  • D. Van Campenhout, T. Mudge, J. P. Hayes. “High-level test generation for design verification of pipelined microprocessors”, The 36th ACM/IEEE Design Automation Conference. June, 1999. New Orleans, Louisiana. pp. 185-188. [pdf]
  • D. Van Campenhout, T. Mudge, K. Sakallah. “Timing verification of sequential dynamic circuits”, IEEE Transactions on Computer-Aided Design. vol 18, no 5. May, 1999. pp. 645-658. [pdf]
  • V. Cuppu, B. Jacob, B. Davis, T. Mudge. “A performance comparison of contemporary DRAM architectures”, The 26th Annual International Symposium on Computer Architecture. May, 1999. pp. 222-233.
  • K. Flautner, G. Tyson, T. Mudge. “MIRVSim: a high level simulator integrated with the MIRV compiler”, Computer Architecture News. vol 27, no 1. March, 1999. pp. 43-46. [Condensed from Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3) at the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998] [pdf]
  • M. Postiff, D. Greene, G. Tyson, T. Mudge. “The limits of instructions level parallelism in SPEC95 applications”, Computer Architecture News. vol 27, no 1. March, 1999. pp. 31-34. [Condensed from Proc. 3rd Workshop on Interaction Between Compilers and Computer Architecture (INTERACT-3) at the 8th Int. Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct. 1998] [pdf]
  • H. Al-Asaad, J. Hayes, T. Mudge. “Modeling and detecting control errors in microprocessors”, International IEEE Conference on DYnamic CONtrol Systems. 1999. [pdf]
  • R. Uhlig, T. Mudge. (Eds.) G. Haring, C. Lindemann, M. Reiser. “Trace-driven memory simulation: A survey”, Springer-Verlag. Performance Evaluation: Origins and Directions. 1999. pp. 97-139. [Abridged from ACM Computing Surveys, vol. 29, no, 2, June 1997, pp. 128-170.]
  • A. Eden, T. Mudge. “The YAGS branch predictor”, 31st Annual IEEE/ACM Symposium on Microarchitecture. December, 1998. pp. 69-77. [pdf]
  • C. Lefurgy, T. Mudge. “Code compression for DSP”, 2nd International Workshop on Compiler and Architecture Support for Embedded Systems. vol 3, no 4. December, 1998. [pdf]
  • D. Van Campenhout, T. Mudge, J. P. Hayes. “High-level test generation for design verification of pipelined microprocessors”, 3rd IEEE International High Level Design Validation and Test Workshop. November, 1998. La Jolla, California. pp. 1-8. [pdf]
  • M. Postiff, D. Greene, G. Tyson, T. Mudge. “The limits of instructions level parallelism in SPEC95 applications”, 3rd Workshop on Interaction Between Compilers and Computer Architecture held in conjunction with the 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. [pdf]
  • K. Flautner, T. Mudge. “Introspective computers”, Wild and Crazy Ideas Session held in conjunction with The 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. [pdf]
  • D. Burger, G. Tyson, T. Austin, J. Smith, T. Mudge.“Alcohol Content vs. Flavor: A Case Study”, Zymurgy Magazine. October, 1998.
  • D. Van Campenhout, T. Mudge, J. P. Hayes. “Evaluation of design error models for verification testing of microprocessors”, IEEE 1st International Workshop on Microprocessor Test and Verification. October, 1998. Washington DC. [pdf]
  • D. Van Campenhout, H. Al-Asaad, J. P. Hayes, T. Mudge, R. Brown. “High-level design verification of microprocessors via error modeling”, ACM Transactions on Design Automation of Electronic Systems. vol 3, no 4. October, 1998. pp. 581-599. [pdf]
  • B. Jacob, T. Mudge. “A look at several memory management units, TLB-refill mechanisms, and page table organizations”, 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. San Jose, California. pp. 295-306. [pdf]
  • K. Flautner, G. Tyson, T. Mudge. “MIRVSim: a high level simulator integrated with the MIRV compiler”, 3rd Workshop on Interaction Between Compilers and Computer Architecture held in conjunction with the 8th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1998. [pdf]
  • B. Jacob, T. Mudge. “Virtual memory in contemporary microprocessors”, Micro. vol 18, no 4. July, 1998. pp. 60-75. [pdf]
  • C-C. Lee, I-C. Chen, T. Mudge. “Design and performance evaluation of global history dynamic branch predictors”, World Multiconference on Systemics Cybernetics and Informatics, and, The 4th International Conference on Information Systems Analysis and Synthesis. vol 2. July, 1998. Orlando, Florida. pp. 664-671. [pdf]
  • B. Jacob, T. Mudge. “Virtual memory: Issues of implementation”, Computer. vol 31, no 6. June, 1998. pp. 33-43. [pdf]
  • R. Brown, B. Bernhardt, M. LaMacchia, J. Abrokwah, P. Parakh, T. Basso, S. Gold, S. Stetson, C. Gauthier, D. Foster, B. Crawforth, T. McQuire, K. Sakallah, R. Lomax, T. Mudge. “Overview of complementary GaAs technology for high-speed VLSI circuits”, IEEE Transactions on VLSI. vol 6, no 1. March, 1998. pp. 47-51. [pdf]
  • C. Lefurgy, P. Bird, I-C. Cheng, T. Mudge. “Improving code density using compression techniques”, 30th Annual IEEE/ACM Symposium on Microarchitecture. December, 1997. pp. 194-203. [pdf]
  • C. Lee, I. Chen, T. Mudge. “The bi-mode branch predictor”, 30th Annual IEEE/ACM Symposium on Microarchitecture. December, 1997. pp. 4-13. [pdf]
  • M. Kelley, M. Postiff, T. Strong, R. Brown, T. Mudge. “A complementary GaAs 32-bit multiply-accumulate unit”, 31st Asilomar Conference on Signals, Systems, and Computers. November, 1997. pp. 1507-1511. [pdf]
  • H. Al-Asaad, D. Van Campenhout, J. Hayes, T. Mudge. “High-level design verification of microprocessors via error modeling”, IEEE International Workshop on High Level Design Validation and Test. November, 1997. pp. 194-201. [pdf]
  • I-C. Chen, C-C. Lee, T. Mudge. “Instruction prefetching using branch prediction information”, International Conference on Computer Design 97. October, 1997. pp. 593-601. [pdf]
  • O. Olukotun, T. Mudge, R. Brown. “Multilevel performance optimization of pipelined caches”, IEEE Transactions on Computers. vol 46, no 10. October, 1997. pp. 1093-1102. [pdf]
  • I-C. Chen, C-C. Lee, M. Postiff, T. Mudge. “Design optimization for high-speed per-address two-level branch predictors”, International Conference on Computer Design 97. October, 1997. pp. 88-96. [pdf]
  • J. Dundas, T. Mudge. “Improving data cache performance by pre-executing instructions under a cache miss”, 1997 ACM International Conference on Supercomputing. July, 1997. pp. 68-75. [pdf]
  • R. Uhlig, T. Mudge. “Trace-driven memory simulation: A survey”, ACM Computing Surveys. vol 29, no 2. June, 1997. pp. 128-170. [pdf]
  • B. Davis, C. Gauthier, P. Parakh, T. Basso, C. Lefurgy, R. Brown, T. Mudge. “Impact of MCMs on high performance processors”, ASME Advances in Electronic Packaging 97. vol 1. June, 1997. pp. 863-868. [pdf]
  • B. L. Jacob, T. Mudge. “Software-managed address translation”, 3rd Symposium on High Performance Computer Architecture. February, 1997. San Antonio, Texas. pp. 156-167. [pdf]
  • R. Uhlig, D. Nagle, T. Mudge, S. Sechrest. “Trap-driven memory simulation with Tapeworm II”, ACM Transactions on Modeling and Computer Simulation. vol 7, no 1. January, 1997. pp. 7-41. [pdf]
  • T. Mudge. “Strategic directions in computer architecture”, ACM Computing Surveys. vol 28, no 4. December, 1996. pp. 671-678. [Also available online to Surveys subscribers via the URL http://www.acm.org/pubs/contents/journals/surveys/1996-28/#4] [pdf]
  • D. Van Campenhout, T. Mudge, K. Sakallah. “Timing verification of sequential domino circuits”, International Conference on CAD. December, 1996. pp. 127-132. [pdf]
  • J. Pierce, T. Mudge. “Wrong path instruction prefetching”, 29th Annual IEEE/ACM Symposium on Microarchitecture. December, 1996. pp. 165-175. [pdf]
  • R. Brown, T. Basso, P. Parakh, S. Gold, C. Gauthier, R. Lomax, T. Mudge. “Complementary GaAs technology for a GHz microprocessor”, Tech. Digest of the GaAsIC Symposium. November, 1996. pp. 313-316. [pdf]
  • B. L. Jacob, T. Mudge. “Support for nomadism in a global environment”, Workshop on Object Replication and Mobile Computing. October, 1996. San Jose, California. [pdf]
  • I-C. Cheng, J. Coffey, T. Mudge. “Analysis of Branch Prediction via Data Compression”, 7th International Conference on Architectural Support for Programming Languages and Operating Systems. October, 1996. pp. 128-137. [pdf]
  • B. Jacob, P. Chen, S. Silverman, T. Mudge. “An analytical model for designing memory hierarchies”, IEEE Transactions on Computers. vol 45, no 10. October, 1996. pp. 1180-1194. [pdf]
  • D. Van Campenhout, T. Mudge, K. Sakallah. “Timing verification of sequential domino circuits”, TechCon 96. September, 1996. [Available as an electronic document to members of Semiconductor Research Corp.] [pdf]
  • B. L. Jacob, T. Mudge. “The trading function in action”, 7th ACM SIGOPS European Workshop. September, 1996. Connemara, Ireland. pp. 241-247. [pdf]
  • R. Brown, J. Hayes, T. Mudge. “Rapid prototyping & evaluation of high-performance computers”, Conference on Experimental Research in Computer Systems, NSF Experimental Systems. June, 1996. Washington DC. pp. 159-168. [pdf]
  • M. Golden, T. Mudge. “A comparison of two common pipeline structures”, Institution of Electrical Engineers Proc.-E, Computers and Digital Techniques. vol 143, no 3. May, 1996. [pdf]
  • T. Mudge. “Position paper: NSF Workshop on Critical Issues”, Computer Architecture Research. May, 1996. [Electronic document]
  • S. Sechrest, C-C. Lee, T. Mudge. “Correlation and aliasing in dynamic branch predictors”, The 23rd Annual International Symposium on Computer Architecture. May, 1996. pp. 22-32. [pdf]
  • T. Mudge. “Panel report: “How can computer architecture researchers avoid becoming the society for irreproducible results?””, Computer Architecture News. vol 24, no 1. March, 1996. pp. 1-5. [pdf]
  • S. Sechrest, C-C. Lee, T. Mudge. “The role of adaptivity in two-level branch prediction”, 28th Annual IEEE/ACM Symposium on Microarchitecture. December, 1995. pp. 264-270. [pdf]
  • D. Van Campenhout, T. Mudge. “Timing Analysis of Digital Systems with Gated Clocks,” Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-257-95, August 1995 [pdf]
  • T. Mudge, I. Chen, J. Coffey. “Limits to Branch Prediction”, Department of Electrical Engineering and Computer Science, The University of Michigan, CSE-TR-282-96. January 1996. [pdf]
  • T. J. Stanley, T. Mudge. “A parallel genetic algorithm for multi-objective microprocessor design”, 6th International Conference on Genetic Algorithms. July, 1995. pp. 597-604. [pdf]
  • K. Sakallah, T. Burks, T. Mudge. “Critical paths in circuits with level-sensitive latches”, IEEE Transactions on VLSI Systems. vol 3, no 2. June, 1995. pp. 273-291. [pdf]
  • R. Uhlig, D. Nagle, T. Mudge, S. Sechrest, J. Emer. “Instruction fetching: Coping with code bloat”, The 22nd Annual International Symposium on Computer Architecture. June, 1995. pp. 345-356. [pdf]
  • B. Davis, T. Mudge. “A Verilog preprocessor for representing datapath components”, 4th International Verilog HDL Conference. March, 1995. pp. 90-98. [pdf]
  • B. Jacob, T. Mudge. “Notes on Calculating Computer Performance”, Department of Electrical and Computer Engineering, The University of Michigan, CSE-TR-231-95, March 1995.[pdf]
  • T. J. Stanley, T. N. Mudge. “A systematic approach to multi-objective computer architecture optimization”, 1995 Conference on Advanced Research in VLSI. March, 1995. pp. 286-300. [pdf]
  • J. Pierce, M. D. Smith, T. Mudge. (Eds.) T. M. Conte, C. E. Gimarc. “Instrumentation tools”, Kluwer Academic Publishers. Fast Simulation of Computer Architectures. 1995. pp. 47-86. [pdf]